1. Field of the Invention
The present invention relates to a phase frequency detector comprising means for providing Up/Down signals in order to detect a phase difference between detector input signals, and output control means having Up/Down signal inputs for providing a detector output signal containing a measure which is proportional to said detected phase difference.
The present invention also relates to a phase locked loop provided with a phase frequency detector and to a communication device provided with a phase frequency detector.
2. Description of the Related Art
Such a phase frequency detector is generally known and is applied in a phase locked loop (PLL), such as described in a McGraw-Hill, Inc. textbook entitled "Phase-Locked Loops" (see FIGS. 3.1 and 3.2). The known phase locked loop comprises a phase frequency detector having two oscillator inputs, a voltage controlled oscillator, and a loop filter interconnecting the detector output and a frequency control input of the voltage controlled oscillator. The oscillator output signal is fed back to the one of the oscillator inputs of the phase frequency detector, whereas its other oscillator input receives another oscillator signal, such as a local oscillator signal from for example a stabile clock oscillator, whereon the PLL locks. The phase frequency detector uses pulse width modulated Up/Down signals to control through a series arrangement of semiconductors the detector output signal, which output signal contains a measure, which is proportional to a detected phase difference between the two oscillator input signals of the detector. Disadvantage of the known phase frequency detector is that its output signal contains a relatively large amount of harmonics requiring averaging by means of the loop filter having a large time constant. However a large time constant reduces the bandwidth and therewith the properties of the PLL to provide a clean, side band frequency reduced and spectral pure VCO signal.